Connections from buried interconnects to device terminals in multiple stacked devices structures

ABSTRACT

In vertically stacked device structures, a buried interconnect and bottom contacts can be formed, thereby allowing connections to be made to device terminals from both below and above the stacked device structures. Techniques herein include a structure that enables electrical access to each independent device terminal of multiple devices, stacked on top of each other, without interfering with other devices and the local connections that are needed.

CROSS REFERENCE TO CO-PENDING APPLICATION

This application is a divisional of U.S. application Ser. No.17/326,449, filed May 21, 2021, which is based upon and claims priorityto U.S. Provisional Patent Application No. 63/085,583 filed Sep. 30,2020, the contents of which are incorporated herein by reference.

FIELD OF THE INVENTION

The disclosure relates to microelectronic devices includingsemiconductor devices, transistors, and integrated circuits, includingmethods of microfabrication.

BACKGROUND

In the manufacture of a semiconductor device (especially on themicroscopic scale), various fabrication processes are executed such asfilm-forming depositions, etch mask creation, patterning, materialetching and removal, and doping treatments. These processes areperformed repeatedly to form desired semiconductor device elements on asubstrate. Historically, with microfabrication, transistors have beencreated in one plane, with wiring/metallization formed above the activedevice plane, and have thus been characterized as two-dimensional (2D)circuits or 2D fabrication. Scaling efforts have greatly increased thenumber of transistors per unit area in 2D circuits, yet scaling effortsare running into greater challenges as scaling enters single digitnanometer semiconductor device fabrication nodes. Semiconductor devicefabricators have expressed a desire for three-dimensional (3D)semiconductor circuits in which transistors are stacked on top of eachother.

One challenge of using 3D semiconductor circuits is having thecapability to electrically isolate and access the gate of each device inthe vertical stack. This access is critical to enable full functionalityof transistor circuits with maximum 3D efficiency. Interconnects areusually formed above the vertical stack, therefore making access to thegates of devices at the bottom of the stack particularly challenging.

SUMMARY

The present disclosure is directed to a semiconductor device comprising:a stack of device tiers having at least three device tiers including alower device tier, one or more intermediate device tiers stackedvertically over the lower device tier, and an upper device tier stackedvertically over the intermediate device tiers, each device tier havingat least one lateral gate-all-around channel of a field effecttransistor; a first interconnect line positioned below the stack ofdevice tiers; a second interconnect line positioned above the stack ofdevice tiers; a bottom contact that connects the first interconnect lineto one or more first device terminals from the stack of device tiers;and a top contact that connects the second interconnect line to one ormore second device terminals from the stack of device tiers.

In one embodiment, the one or more first device terminals is a lowerdevice terminal in the lower device tier.

In one embodiment, the one or more first devices terminals and the oneor more second device terminals is a gate.

In one embodiment, the one or more second device terminals is at leastone of an upper device terminal in the upper device tier and anintermediate device terminal in the one or more intermediate devicetiers.

In one embodiment, in a case that the one or more second deviceterminals includes the intermediate device terminal, the intermediatedevice terminal is laterally extended beyond a length of (1) the upperdevice terminal and (2) any additional intermediate device terminalsfrom the one or more intermediate device tiers located above theintermediate device terminal to connect the top contact to theintermediate device terminal without contacting the additionalintermediate device terminals nor the upper device terminal.

In one embodiment, at least one of vertically adjacent device tiers inthe stack of device tiers shares a common device terminal.

One embodiment further comprises insulation material located between andelectrically separating device terminals of at least one pair ofvertically adjacent device tiers in the stack of device tiers.

One embodiment further comprises a power rail positioned to providepower to the stack of device tiers.

In one embodiment, the one or more first device terminals and the one ormore second device terminals is at least one of a source and drain.

The present disclosure is also directed to a method of forming asemiconductor device, the method comprising: forming a stack ofnano-channels spaced vertically from each other; forming a firstinterconnect line positioned below the stack of nano-channels; creatinga bottom contact that connects to the first interconnect line; forminggate-all-around channels from the stack of nano-channels, wherein thegate-all-around channels form a stack of device tiers having at leastthree device tiers including a lower device tier, one or moreintermediate device tiers stacked vertically over the lower device tier,and an upper device tier stacked vertically over the one or moreintermediate device tiers; connecting the first interconnect line to oneor more first device terminals from the stack of device tiers using thebottom contact; and connecting a second interconnect line to one or moresecond device terminals from the stack of device tiers using a topcontact, the second interconnect line formed above the stack of devicetiers.

In one embodiment, the one or more first device terminals is a lowerdevice terminal in the lower device tier.

In one embodiment, the one or more first device terminals and the one ormore second device terminals is a gate.

In one embodiment, the one or more second device terminals is at leastone of an upper device terminal in the upper device tier and anintermediate device terminal in the one or more intermediate devicetiers.

One embodiment further comprises, in a case that the one or more seconddevice terminals includes the intermediate device terminal, laterallyextending the intermediate device terminal beyond a length of (1) theupper device terminal and (2) any additional intermediate deviceterminals from the one or more intermediate device tiers located abovethe intermediate device terminal to connect the top contact to theintermediate device terminal without contacting the additionalintermediate device terminals nor the upper device terminal.

One embodiment further comprises forming a power rail positioned toprovide power to the stack of device tiers.

In one embodiment, the creating the bottom contact includes forming apattern of the bottom contact, filling the pattern with sacrificialmaterial, and replacing the sacrificial material with metal.

In one embodiment, the forming the first interconnect includes forming apattern of the first interconnect, filling the pattern with sacrificialmaterial, and replacing the sacrificial material with metal.

In one embodiment, the one or more first device terminals and the one ormore second device terminals is at least one of a source and drain.

In one embodiment, at least one of vertically adjacent device tiers inthe stack of device tiers shares a common device terminal.

One embodiment further comprises electrically separating deviceterminals of at least one of vertically adjacent device tiers in thestack of device tiers using insulation material.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1A shows an example of an N-type metal oxide semiconductortransistor (NMOS) connected together with a P-type metal oxidesemiconductor transistor (PMOS) using a horizontal common gate,according to one embodiment of the present disclosure.

FIG. 1B shows an example of an NMOS connected together with a PMOS usinga vertical common gate (i.e. a CFET), according to one embodiment of thepresent disclosure.

FIG. 2 shows an example of complementary field effect transistor (CFET)on CFET stacking, according to one embodiment of the present disclosure.

FIG. 3A shows a layout view of a circuit having gate connections to afirst interconnect line below a stack of devices using a bottom gateconnect, and a second interconnect line above the stack of devices usinga top gate contact, according to one embodiment of the presentdisclosure.

FIG. 3B shows perspective view of the circuit in FIG. 3A, according toone embodiment of the present disclosure.

FIG. 4 is a flowchart of a method for creating a circuit having gateconnections to a first interconnect line below a stack of devices usinga bottom gate connect, and a second interconnect line above the stack ofdevices using a top gate contact, according to one embodiment of thepresent disclosure.

FIG. 5 is a flowchart of a method for forming a first interconnect linepositioned below the stack of devices, according to one embodiment ofthe present disclosure.

FIG. 6 is a flowchart of a method for creating bottom gate contacts,according to one embodiment of the present disclosure.

FIG. 7 is a flowchart of a method for forming gate-all-around channels,according to one embodiment of the present disclosure.

FIG. 8A illustrates active stack formation, according to one embodimentof the present disclosure, according to one embodiment of the presentdisclosure.

FIG. 8B illustrates active stack pattering, according to one embodimentof the present disclosure, according to one embodiment of the presentdisclosure.

FIG. 8C illustrates buried power rail formation, according to oneembodiment of the present disclosure.

FIG. 8D illustrates buried interconnect trench formation, according toone embodiment of the present disclosure.

FIG. 8E illustrates buried interconnect formation, according to oneembodiment of the present disclosure.

FIG. 8F illustrates bottom gate contact patterning, according to oneembodiment of the present disclosure.

FIG. 9A illustrates a bottom gate contact oxide etch, according to oneembodiment of the present disclosure.

FIG. 9B illustrates bottom gate contact metallization, according to oneembodiment of the present disclosure.

FIG. 9C illustrates an oxide gap fill, according to one embodiment ofthe present disclosure.

FIG. 9D illustrates revealing the active stack and bottom gate contact,according to one embodiment of the present disclosure.

FIG. 9E illustrates dummy gate formation, according to one embodiment ofthe present disclosure.

FIG. 9F illustrates surface planarization to open access to dummy gates,according to one embodiment of the present disclosure.

FIG. 10A illustrates dummy gate removal, according to one embodiment ofthe present disclosure.

FIG. 10B illustrates a channel release, according to one embodiment ofthe present disclosure.

FIG. 10C illustrates gate stack formation, according to one embodimentof the present disclosure.

FIG. 10D illustrates final gate metallization of the tier 1 and tier 2devices, according to one embodiment of the present disclosure.

FIG. 10E illustrates final gate metallization of the tier 3 and tier 4devices, according to one embodiment of the present disclosure.

FIG. 10F illustrates a final structure, according to one embodiment ofthe present disclosure.

FIG. 11A shows a zoomed in view during dummy gate removal, according toone embodiment of the present disclosure.

FIG. 11B shows a zoomed in view during channel releases, according toone embodiment of the present disclosure.

FIG. 11C shows a zoomed in view during interlayer (IL)/high-k (HK)formation, according to one embodiment of the present disclosure.

FIG. 11D shows a zoomed in view during metal 1 formation, according toone embodiment of the present disclosure.

FIG. 11E shows a zoomed in view during metal 2 formation, according toone embodiment of the present disclosure.

FIG. 11F shows a zoomed in view during metal 3 formation, according toone embodiment of the present disclosure.

DETAILED DESCRIPTION

As the semiconductor industry transitions to a new device architecture,from finFET to lateral gate-all-around nano-sheet (LGAA NS), there is asignificant research focus on the complementary FET device architecture,or CFET. In conventional technology, that is, planar bulk and finFET,NMOS 103 and PMOS 101 are built and arranged side-by-side on the sameplane of the silicon wafer with a horizontal common gate 105, as shownin FIG. 1A. As shown in FIG. 1B, CFET takes advantage of the verticaldimension by stacking the NMOS 103 on top of the PMOS 101 (or viceversa). A vertical common gate 107 between the NMOS 103 and PMOS 101replaces the horizontal common gate 105 running from the NMOS 103 sideto the PMOS 101 side to make the complementary functions of CMOS. Thisphysical arrangement takes advantage of the vertical dimension toprovide better power, performance and area (PPA) scaling. The CFETarchitecture considered herein is based on, but not limited to, the LGAANS device architecture, which is nano-sheet (i.e. nano-channel) stackedon nano-sheet (instead of finFET stacked on finFET).

This disclosure is related to vertically stacking CFETs to offer compact3D circuits that can lead to fundamental changes in the way circuits aredesigned. FIG. 2 shows a simplified representation of CFET 201 on CFET203 stacking. Some details can be seen, such as the order of the tackedtransistors (PMOS/NMOS/PMOS/NMOS from bottom to top), or the verticalgates being common to all the stacked devices. But such details areobviously very flexible and therefore highlight the very high number ofcombinations that 3D opens up.

As previously mentioned, stacking CFETs vertically presents challenges.One particular challenge is having the capability to electricallyisolate and access the gate of each device in the stack. In such acomplex stack, as described in FIG. 2 , getting access to devices at thebottom of the stack (e.g. PMOS of CFET 203) is a challenge. This isbecause connections are conventionally made from the top of the stack.

The use case presented herein, for multiple layers of active devicesstacked on top of each other, is naturally more challenging. Techniquesherein, however, provide a unique structural solution with multipleassociated methods. Techniques herein include a structure that enableselectrical access independently to each gate of multiple devices,stacked on top of each other, without interfering with other devices andthe local connections that are needed. In particular, structures hereinprovide access to the lowest device of the stack, which can be the mostchallenging to access in many instances. Techniques herein solve thisproblem by leveraging the vertical dimension to enable fullfunctionality of CMOS circuits. This design furthers the pursuit ofhighly efficient, 3D stacked and integrated structures, therebyimproving power, performance and area. In one embodiment, a structuralconductor element is provided that the multiple device stack canconveniently connect to vertically.

The ability to electrically access the gates of the different devicetiers, and to independently access to some extent, is beneficial toenable efficient 3D designs. Techniques herein enable stacking CFET ontop of CFET with very dense designs. The discussions herein willprimarily discuss using bottom gate contacts and top gate contacts toconnect to gates, but it should be understood that these techniques canalso be applied to make connections between top contacts and bottomcontacts to other device terminals, such as the source and drain (e.g.bottom source contacts, top source contacts, bottom drain contacts, topdrain contacts).

FIG. 3A and FIG. 3B show a logic circuit made with four stacked levelsof transistors incorporating techniques described herein. FIG. 3A showsa simplified top down view, or layout representation of that circuit.FIG. 3B shows a simplified 3D view of the 3D structure of that circuit,highlighting a central element of techniques herein, which is the bottomgate contact 819. Also shown are a first tier of devices 835, secondtier of devices 837, third tiers of devices 839, fourth tier of devices841, first interconnect line 813 connected to a gate of the first tierof devices 835 using the bottom gate contacts 819, and top gate contacts845 connecting a second interconnect line 849 located above the tier ofdevices 835, 837, 839, 841 to various device gates in the second tier ofdevices 837, third tier of devices 839, and fourth tier of devices 841.Each device in the four tiers of devices 835, 837, 839, 841 are made oftwo gate-all-around channels 823, though more or less can be used inother embodiments.

As can be seen from the layout view in FIG. 3A, there are only fourmetal tracks available from the metal interconnect level on top of thestructure (i.e. second interconnect line 849). This limited number is adirect result of the scaling trend impacting logic circuits. The numberof tracks is a direct measure of the cell height, which has a directimpact on the cell area. Therefore reducing the cell height inconventional technology is done by reducing the number of tracks.

This cell compaction, however, creates additional challenges. Thiscompaction makes it more difficult to provide all connectivity necessaryto obtain a functional cell. Indeed, there are not enough metal tracksavailable to connect the devices together from the outside, asillustrated with the second interconnect line 849 in FIG. 3A and FIG.3B. Typically, this vertical compaction would lead to a relaxation inthe other direction (i.e. the width of the cell needs to grow to enablethe connectivity needed). Unfortunately, increased cell width defeatsthe intent of density scaling.

On the layout view of FIG. 3A, the white squares represent the top gatecontacts 845, which connect the devices to the outside through thesecond interconnect line 849. The dashed line 851 represents where thecross-section shown in FIG. 3B is located. As can be seen along the line851, there are four squares representing bottom gate contacts 819. It ishard to represent on a 2D layout view, but there are also four squaresrepresenting top gate contacts 845 matching exactly the location of thefour squares representing the bottom gate contacts 819 along the dashedline 851. The view on FIG. 3B illustrates how these two types of gatecontacts are stacked on top of each other to complete the logic functionof this particular circuit. On this particular cross-section, it can beseen that the top gate contacts 845 are used to connect the secondinterconnect line 849 to the gates of the second tier of devices 837.Note that alternatively this can instead connect with the gates of thethird tier of devices 839 or the fourth tier of devices 841 (as can beseen in the background of FIG. 3B). The bottom gate contacts 819 areused to connect the gates of the first tier of devices 835 to a buriedinterconnect level, also referred to herein as the first interconnectline 813. This first interconnect line 813 is a buried metalinterconnect line positioned below the tiers of devices 835, 837, 839,841. Note that in one embodiment, the shape of certain device gates canbe modified to offset a distance from one another to provide easieraccess for top and/or bottom gate contacts to make connections; suchtechniques will be discussed in more detailed herein below. The abilityto connect the gates of the lowest device tier to a set of interconnectsdifferent from the conventional interconnect techniques is beneficial.This technique herein relaxes the density of connections that theconventional top interconnect has to provide and ultimately enableshighly efficient and compact 3D designs.

While the first interconnect line 813 itself is beneficial in that iteffectively provides a new layer of metal interconnects or extra tracksto complete the cell, providing a way herein to use this buriedinterconnect, that is, the bottom gate contact, is valuable. Althoughdescription of embodiments herein center around connecting the gateterminals of the first tier of devices 835 with bottom gate contact 819,it should be noted that the techniques herein also extend to connectingany device terminals of the first device tier as well. For example, thedevice terminal can be a source or drain connecting to the firstinterconnect line 813 through a bottom active contact similar to thebottom gate contact 819. Note also that examples herein feature a buriedpower rail and power wall; these features, however, are optional forembodiments herein.

Additionally, pairs of vertically adjacent gates can be electricallyseparated, or share a common terminal. For example, as can be seen inFIG. 3B, insulation material 847 is located between some gates of thefirst tier of devices 835 and second tier of devices 837, as well asbetween the gates of the second tier of devices 837 and third tier ofdevices 839, to provide electrical separation. Furthermore, gates of thethird tier of devices 839 and fourth tier of devices 841 are notelectrically separated, but rather share a common gate terminal. It canbe appreciated that in other embodiments, any combination of sharingand/or separating of gate terminals can be utilized.

The second interconnect line 849 can be connected to devices in thefourth tier of devices 841, third tier of devices 839, second tier ofdevices 837 and/or first tier of devices 835 using top gate contacts.The first interconnect line 813 can be connected to devices in the firsttier of devices 835 using bottom gate contacts.

Furthermore, the various device terminals can be altered to protrude(i.e. offset), providing a convenient opening for a connection between adevice terminal and the first or second interconnect line. For example,as shown in the particular cross-sectional view of FIG. 3B, the gateterminals for the first tier of devices 835 and second tier of devices837 have been laterally extended length-wise to protrude beyond the gateterminals of the third tier of devices 839 and fourth tier of devices841, thereby enabling a portion of the top gate contacts 845 to connectthe gate terminal of the second tier of devices 837 to the secondinterconnect line 849 in a direct path without touching the third tierof devices 839 and the fourth tier of devices 841. This lateralextension can be made possible by: (1) growing the gates of the firsttier of devices 835 and the second tier of devices 837, (2) trimmingdown the gates of the third tier of devices 839 and fourth tier ofdevices 841, or (3) a combination thereof.

In one embodiment, it can be appreciated that the present disclosure canbe viewed as a method. FIG. 4 is a flowchart outlining one embodiment ofa method 400. Discussion of method 400 will be supplemented withexemplary process flow illustrations as shown in FIGS. 8A-8F, 9A-9F,10A-10F, and 11A-11F, as well as reference to sub-methods of method 400using FIGS. 5, 6 and 7 .

Step 410 is forming a stack of nano-channels spaced vertically from eachother. An active layer stack can be formed, such as alternating layersof semiconductor material (e.g. Si, Ge, SiGe) grown epitaxially. Anexample of step 410 is shown in FIG. 8A, illustrating formation of anactive stack 801 comprising silicon nano-channels 803 and sacrificialmaterial 805 above bulk silicon 807.

Step 420 is forming a first interconnect line positioned below the stackof nano-channels. The first interconnect line is formed below the stackof nano-channels so that when the stack of nano-channels are later usedto form a vertical stack of devices, device gates can be connected tothe first interconnect line using a bottom gate contact. This allowsgate connections to be made from below the stack, which in turn givesmore space for gate connections to be made from the top of the stack.

FIG. 5 shows a flowchart of a sub-method for performing step 420. Step421 is patterning the stack formed in step 410 by masking and etchingthe stack. For example, the patterning can form a fin structure havingmultiple sheets of alternating materials for nano-channels. An exampleof step 421 is shown in FIG. 8B, where the stack 801 has been masked andetched to form a fin structure having multiple sheets of alternatingmaterials for the nano-channels 803.

Step 422 is forming a power rail. The power rail can be formed anywherenearby (e.g. above, below, adjacent) the stack of nano-channels. In oneembodiment, the power rail can be formed at least partially within bulkmaterial below the stack. In another embodiment, this step can beomitted. An example of step 422 is shown in FIG. 8C, where a buriedpower rail 809 is formed at least partially in the bulk silicon 807below the stack 801.

Step 423 is forming trenches for the first interconnect line. Trenchescan be formed below and adjacent to (offset from) the nano-channels ofthe stack. The trenches can be formed at least partially within bulkmaterial. An example of step 423 is shown in FIG. 8D, where trenches 811are formed adjacent to the nano-channels 803 and partially within thebulk silicon 807.

Step 424 is forming the first interconnect line. The trenches formed instep 423 are metallized and thereby form the first interconnect line, tobe later connected to gates of lower tier devices. Various metals can beused, such as ruthenium, which enables selective deposition to mitigateoverburden to be removed. In addition, after the trench is filled, themetal can be capped, and a dielectric can be deposited on the substrateto fill openings above the first interconnect line used to create thetrenches. An example of step 424 is shown in FIG. 8E, where the trenches811 from FIG. 8D have been partially metallized and capped to form afirst interconnect line 813, and a dielectric is deposited to fill thetrenches 811 above the first interconnect line 813.

Returning back to FIG. 4 , step 430 is creating bottom gate contactsthat connect to the first interconnect line. The purpose of creating thebottom gate contact is to connect one or more gates of lower tierdevices (formed later) to the first interconnect line formed in step420.

FIG. 6 shows a flowchart of a sub-method for performing step 430. Step431 is bottom gate contact patterning. A pattern can be used for formingbottom gate contact openings. These are similar to vias that connect thefirst interconnect line to the bottom gates once they have been formed.An example of bottom gate contact patterning is shown in FIG. 8F, wherea bottom gate contact pattern 815 is shown.

Step 432 is forming openings for bottom gate contacts. In oneembodiment, an oxide etch can be performed using the bottom gate contactpattern from step 431. An example of this step is shown in FIG. 9A,where openings 817 are etched and transferred to reflect the bottom gatecontact pattern 815 from FIG. 8F. The openings 817 partially expose thefirst interconnect line 813.

Step 433 is bottom gate contact metallization. Bottom gate contactopenings formed in step 432 are metallized, that is, a conductor isextended from the buried first interconnect line to one or morelocations above the buried first interconnect line for later connectionto gates in lower device tiers. An example is shown in FIG. 9B, wheremetal is partially formed in the openings 817 on the first interconnectline 813, thereby creating bottom gate contacts 819 extended above andconnected to the first interconnect line 813.

Step 434 is performing an oxide gap fill, though in other embodiments,this step can be omitted. The openings above the newly formed bottomgate contacts can be filled with oxide. An example is shown in FIG. 9C,where remaining (non-metallized) portions of the openings 817 above thebottom gate contacts 819 from FIG. 9B have been filled with oxide.

Step 435 is revealing the active stack and bottom gate contacts. Oxideor dielectric is etched until uncovering the bottom gate contacts andthe stack of nano-channels. This can be executed with an oxide recessetch, for example. The uncovered height of the bottom gate contacts canbe approximately 5-20 nanometers according to one embodiment, thoughthis height can vary in other embodiments. An example is shown in FIG.9D, where the etching has been performed to reveal the stack 801 andbottom gate contacts 819, the bottom gate contacts 819 being partiallyexposed above the bulk silicon 807 and shallow trench isolation 820.

Referring back to FIG. 4 , step 440 is forming gate-all-around channelsfrom the stack of nano-channels. The gate-all-around channels can beused later as channels for devices of various tiers. As appreciated byone of skill in the art, the number of gate-all-around channels used forforming each tier of devices can vary.

FIG. 7 shows a flowchart of a sub-method for performing step 440. Step441 is dummy gate formation. For brevity, because dummy gate formationis not a new concept, detailed discussion is omitted. It can beappreciated that any technique known by one of skill in the art can beused for forming the dummy gates. The dummy gate material can be indirect contact with the revealed height of the bottom gate contacts. Anexample of step 441 is shown in FIG. 9E, where the dummy gates 821 arein contact with the bottom gate contacts 819.

Step 442 is performing surface planarization. With access to the dummygate material, a conventional replacement metal gate (RMG) flow can befollowed according to one embodiment. An example of step 442 is shown inFIG. 9F. FIG. 9F shows open access to the dummy gates 821 after surfaceplanarization. In addition, note that the power rail 809 has beenextended upwards, essentially creating a power wall. Note that formationof the power rail 809 can be omitted in other embodiments.

Step 443 is dummy gate removal. The RMG flow can include selectivelyremoving dummy gate material using etch processes known by one of skillin the art. An example of step 443 is shown in FIG. 10A, where the dummygates 821 from FIG. 9F have been selectively removed. Removal of thedummy gate material reveals again the top of the bottom gate contacts819.

Step 444 is performing a channel release etch. Once the dummy gatematerial is selectively removed, a channel release etch is executed toremove the sacrificial material between nano-channels. In oneembodiment, this selective, isotropic etch can be executed usingvapor-phase etching, which is known to be able to target onesemiconductor material while leaving other semiconductor materials. Anexample of step 444 is shown in FIG. 10B, where sacrificial material 805is removed between the nano-channels 803, thereby exposing the siliconnano-channels 803.

Step 445 is gate stack formation for the different devices in the stack.The gate dielectric materials (interlayer (IL) and high-k (HK)) aredeposited by selective deposition on the nano-channels only, withoutforming on the uncovered top of the bottom gate contacts. Thereafter,depending on the type of metallization selected for each of the metalsneeded for the gate stack, the uncovered top of the bottom gate contactswill be covered with all or only some of these metals. An example isshown in FIG. 10C, where gate stack formation has been executed, therebycreating four tiers of devices (one lower device tier, two intermediatedevice tiers, and one upper device tier), each device tier having twogate-all-around channels 823.

FIG. 11A-11F show a zoomed in view of the revealed top of the bottomgate contact 819 in FIGS. 10A, 10B, and 10C during steps 443, 444, and445. FIG. 11A shows a close up of the bottom gate contact 819 afterdummy gate removal in step 443. As shown, the bottom gate contact 819 ispartially exposed. FIG. 11B shows the same view after a channel releasehas been performed in step 444, thereby exposing the nano-channels 803.FIG. 11C shows IL 825 and HK 827 formed selectively on the siliconnano-channels 803. HK 827 is the outer layer relative to the IL 825.

FIG. 11D shows a first metal 829 (e.g. TiN, TaN, TiAl) depositedselectively only on the HK 827, and not covering the revealed top of thebottom gate contact 819 (though it would be fine if it did). FIG. 11Eshows a second metal 831 (e.g. TiN, TaN, TiAl) deposited selectively onthe first metal 829. This second metal 831 can cover the revealed top ofthe bottom gate contact 819. FIG. 11F shows a third metal 833 (e.g. TiN,TaN, TiAl) deposited selectively on the second metal 831, therebycompleting gate stack formation.

It should be noted that if the liner (e.g. TiN) of the revealed top ofthe bottom gate contacts via is removed by an isotropic etch, leavingonly the core metal exposed (e.g. Ru), then the number of metalinterfaces on the revealed top of the bottom gate contacts can belimited.

Referring back to FIG. 4 , step 450 is connecting one or more gates inthe lower tier of devices to the first interconnect line using thebottom gate contact. This can include lower gate metallization, wheregates of the lower tier devices are metallized with final metal, such astungsten (W) or ruthenium (Ru). This final metal connects to theuncovered top of the bottom gate contacts, thereby establishing contactbetween the actual device gates in the lower tier devices and the firstinterconnect line through the uncovered top of the bottom gate contacts.

Step 460 is connecting one or more gates in the intermediate tier ofdevices to the second interconnect line formed above the stack of devicetiers. In other words, metallized gates for devices verticallypositioned between lower and upper tier devices can be connected to thesecond interconnect line located above the upper-most device tier.Connections to the second interconnect line can be made usingconventional top gate contacts. In embodiments where there are nointermediate devices, this step can be omitted.

Step 470 is connecting one or more upper gates in the upper tier ofdevices to the second interconnect line using a top gate contact,thereby forming the final structure. Because some connections were madeusing the first interconnect line, there is more room for connectionsbetween gates of upper/intermediate tier devices and the second metalinterconnect line. These connections can be made using conventional topgate contacts.

An example of steps 450-470 are shown in FIG. 10D-10F. In FIG. 10D, thegate of a first tier of devices 835 and gate of a second tier of devices837 have been metallized with a final metal 843 (e.g. W, Ru). Some ofthis final metal 843 connects to the uncovered top of the bottom gatecontacts 819, thus establishing contact between the actual device gateof the first tier of devices 835 and the first interconnect line 813through the uncovered top of the bottom gate contacts 819. In FIG. 10E,final metallization has been executed for the third tier of devices 839and the fourth tier of devices 841. The final structure is shown in FIG.10F. One of the top gate contacts 845 is connecting the gate of thesecond tier of devices 837 and the second interconnect line 849, whileone of the bottom gate contacts 819 connecting the gate of the firsttier of devices 835 and the first interconnect line 813.

As can be appreciated, many different combinations of gate contacts canbe formed to various tiers from either top or buried interconnects inother embodiments.

In one embodiment, the bottom gate contacts in step 433 are initiallyformed with a sacrificial material instead of metal. This sacrificialmaterial is then uncovered in step 443 during dummy gate removal. Thesacrificial material is then selectively removed before the IL/HKselective formation. Alternatively, this sacrificial material can be thesame material as the dummy gate material, and be removed together withthe dummy gate in step 443. The bottom gate contacts then receive finalmetallization during gate stack metal deposition.

In one embodiment, back side processing can be utilized. For example,the bottom gate contacts can be printed directly from a back side of thewafer, or the buried interconnects and the bottom gate contacts can beprinted together from a back side of the wafer in a dual damascenetechnique. As another example, the bottom gate contacts and buriedinterconnects can be printed on the front side of the wafer and filledwith sacrificial material. The bottom gate contacts and buriedinterconnects can then be revealed during backside processing. Thesacrificial material can be removed from both buried interconnect andbottom gate contacts, then metallized together, akin to a dual damasceneapproach. In another embodiment, the bottom gate contacts can be printeddirectly through the dummy gate cavity after dummy gate removal in step443.

It can be appreciated that the present disclosure can also be viewed assystem. In one embodiment, the system is a semiconductor devicecomprising: a stack of device tiers having at least three device tiersincluding a lower device tier, one or more intermediate device tiersstacked vertically over the lower device tier, and an upper device tierstacked vertically over the intermediate device tiers, each device tierhaving at least one lateral gate-all-around channel of a field effecttransistor; a first interconnect line positioned below the stack ofdevice tiers; a second interconnect line positioned above the stack ofdevice tiers; a bottom contact that connects the first interconnect lineto one or more first device terminals from the stack of device tiers;and a top contact that connects the second interconnect line to one ormore second device terminals from the stack of device tiers. Exemplarysystems are represented in FIGS. 3A, 3B, and 10F, which were previouslydiscussed.

As previously discussed, the system can be viewed in many embodiments.For example, an intermediate device terminal in the one or moreintermediate device tiers can be connected to the second interconnectline.

In another embodiment, the system includes a power rail. The power railcan provide power to the stack of device tiers, and be positioned in amyriad of locations, such as above the stack of device tiers, below thestack of device tiers, or next to the stack of device tiers.

In one embodiment, the device terminals connected to the top and/orbottom contact is a gate. In other embodiments, the device terminalsconnected to the top and/or bottom contact is a source or drain.

Those skilled in the art will also understand that there can be manyvariations made to the operations of the techniques explained abovewhile still achieving the same objectives of the invention. Suchvariations are intended to be covered by the scope of this disclosure.The order of discussion of the different steps as described herein hasbeen presented for clarity sake. In general, these steps can beperformed in any suitable order. Additionally, although each of thedifferent features, techniques, configurations, etc. herein may bediscussed in different places of this disclosure, it is intended thateach of the concepts can be executed independently of each other or incombination with each other. As such, the foregoing descriptions ofembodiments of the invention are not intended to be limiting. Rather,any limitations to embodiments of the invention are presented in thefollowing claims.

Embodiments of the present disclosure may also be as set forth in thefollowing parentheticals.

(1) A semiconductor device comprising: a stack of device tiers having atleast three device tiers including a lower device tier, one or moreintermediate device tiers stacked vertically over the lower device tier,and an upper device tier stacked vertically over the intermediate devicetiers, each device tier having at least one lateral gate-all-aroundchannel of a field effect transistor; a first interconnect linepositioned below the stack of device tiers; a second interconnect linepositioned above the stack of device tiers; a bottom contact thatconnects the first interconnect line to one or more first deviceterminals from the stack of device tiers; and a top contact thatconnects the second interconnect line to one or more second deviceterminals from the stack of device tiers.

(2) The semiconductor device of (1), wherein the one or more firstdevice terminals is a lower device terminal in the lower device tier.

(3) The semiconductor device of any (1) to (2), wherein the one or morefirst device terminals and the one or more second devices terminals is agate. (4) The semiconductor device of any (1) to (3), wherein the one ormore second device terminals is at least one of an upper device terminalin the upper device tier and an intermediate device terminal in the oneor more intermediate device tiers.

(5) The semiconductor device of any (1) to (4), wherein, in a case thatthe one or more second device terminals includes the intermediate deviceterminal, the intermediate device terminal is laterally extended beyonda length of (1) the upper device terminal and (2) any additionalintermediate device terminals from the one or more intermediate devicetiers located above the intermediate device terminal to connect the topcontact to the intermediate device terminal without contacting theadditional intermediate device terminals nor the upper device terminal.

(6) The semiconductor device of any (1) to (5), wherein at least one ofvertically adjacent device tiers in the stack of device tiers shares acommon device terminal.

(7) The semiconductor device of any (1) to (6), further comprisinginsulation material located between and electrically separating deviceterminals of at least one pair of vertically adjacent device tiers inthe stack of device tiers.

(8) The semiconductor device of any (1) to (7), further comprising apower rail positioned to provide power to the stack of device tiers.

(9) The semiconductor device of any (1) to (8), wherein the one or morefirst device terminals and the one or more second device terminals is atleast one of a source and drain.

(10) A method of forming a semiconductor device, the method comprising:forming a stack of nano-channels spaced vertically from each other;forming a first interconnect line positioned below the stack ofnano-channels; creating a bottom contact that connects to the firstinterconnect line; forming gate-all-around channels from the stack ofnano-channels, wherein the gate-all-around channels form a stack ofdevice tiers having at least three device tiers including a lower devicetier, one or more intermediate device tiers stacked vertically over thelower device tier, and an upper device tier stacked vertically over theone or more intermediate device tiers; connecting the first interconnectline to one or more first device terminals from the stack of devicetiers using the bottom contact; and connecting a second interconnectline to one or more second device terminals from the stack of devicetiers using a top contact, the second interconnect line formed above thestack of device tiers.

(11) The method of (10), wherein the one or more first device terminalsis a lower device terminal in the lower device tier.

(12) The method of any (10) to (11), wherein the one or more firstdevice terminals and the one or more second device terminals is a gate.

(13) The method of any (10) to (12), wherein the one or more seconddevice terminals is at least one of an upper device terminal in theupper device tier and an intermediate device terminal in the one or moreintermediate device tiers.

(14) The method of any (10) to (13), further comprising, in a case thatthe one or more second device terminals includes the intermediate deviceterminal, laterally extending the intermediate device terminal beyond alength of (1) the upper device terminal and (2) any additionalintermediate device terminals from the one or more intermediate devicetiers located above the intermediate device terminal to connect the topcontact to the intermediate device terminal without contacting theadditional intermediate device terminals nor the upper device terminal.

(15) The method of any (10) to (14), further comprising forming a powerrail positioned to provide power to the stack of device tiers.

(16) The method of any (10) to (15), wherein the creating the bottomcontact includes forming a pattern of the bottom contact, filling thepattern with sacrificial material, and replacing the sacrificialmaterial with metal.

(17) The method of any (10) to (16), wherein the forming the firstinterconnect includes forming a pattern of the first interconnect,filling the pattern with sacrificial material, and replacing thesacrificial material with metal.

(18) The method of any (10) to (17), wherein the one or more firstdevice terminals and the one or more second device terminals is at leastone of a source and drain.

(19) The method of any (10) to (18), wherein at least one of verticallyadjacent device tiers in the stack of device tiers shares a commondevice terminal.

(20) The method of any (10) to (19), further comprising electricallyseparating device terminals of at least one of vertically adjacentdevice tiers in the stack of device tiers using insulation material.

1. A method of forming a semiconductor device, the method comprising:forming a stack of nano-channels spaced vertically from each other;forming a first interconnect line positioned below the stack ofnano-channels; creating a bottom contact that connects to the firstinterconnect line; forming gate-all-around channels from the stack ofnano-channels, wherein the gate-all-around channels form a stack ofdevice tiers having at least three device tiers including a lower devicetier, one or more intermediate device tiers stacked vertically over thelower device tier, and an upper device tier stacked vertically over theone or more intermediate device tiers; connecting the first interconnectline to one or more first device terminals from the stack of devicetiers using the bottom contact; and connecting a second interconnectline to one or more second device terminals from the stack of devicetiers using a top contact, the second interconnect line formed above thestack of device tiers.
 2. The method of claim 1, wherein the one or morefirst device terminals is a lower device terminal in the lower devicetier.
 3. The method of claim 1, wherein the one or more first deviceterminals and the one or more second device terminals is a gate.
 4. Themethod of claim 1, wherein the one or more second device terminals is atleast one of an upper device terminal in the upper device tier and anintermediate device terminal in the one or more intermediate devicetiers.
 5. The method of claim 4, further comprising, in a case that theone or more second device terminals includes the intermediate deviceterminal, laterally extending the intermediate device terminal beyond alength of (1) the upper device terminal and (2) any additionalintermediate device terminals from the one or more intermediate devicetiers located above the intermediate